Clocking variations outside of functional mode, i.e., normal memory operation, at times cause memory array contents to be corrupted when exercising, e.g., a memory's, such as a cache's, modified write feature during, e.g., known Level-Sensitive Scan Design (LSSD) and Common On-chip Processor (COP) modes.
The modified write feature allows data read from the memory array to be modified by incoming data and written back into the array within the same cycle. By definition, this architecture forces the write operation to the end of the cycle in the event of a read/modified write operation. Implementation of this architecture required that the modified write, controls and the write operation itself be enabled by the falling edge of the clock, i.e., the half cycle boundary, and disabled on the rising edge of the clock allowing for the restore of the array, including word lines, bit lines, sense amplifiers and the write-heads.
In the functional mode the system clock is free running. The write operation is enabled on the falling edge and disabled along with the array on the rising edge of the clock pulse.
In LSSD test and COP modes the free running memory clock is interrupted while new data and controls are being generated for the next memory cycle. During the interrupt period the clock remains low and the memory is active until the next rising clock edge at which time the memory restores. It is during this period, i.e., from the falling to the rising clock edges, that the data and the controls to the memory must be held valid. Any change to either the data or the controls during modified write corrupts the array contents.
U.S. Pat. No. 5,031,141, by D. Guddat et al, which issued on Jul. 9, 1991, discloses apparatus for generating self-timing for on-chip cache wherein write operations occur in the second phase of the clock cycle, generated by a signal indicating a hit and a write signal, which may exceed the second phase of the cycle.
In U.S. Pat. No. 5,091,889, by T. Hamano et al, which issued Feb. 25, 1992, there is disclosed a semiconductor memory having an operation margin against a write recovery time wherein address transition detecting circuits are used.
U.S. Pat. No. 5,204,841, by B. A. Chappell et al, which issued on Apr. 20, 1993, teaches a virtual multi-port RAM employing input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle incorporating a static RAM segmented into many input triggered self-resetting, fast cycling blocks.
In U.S. Pat. No. 5,235,543, by E. E. Rosen, which issued Aug. 10, 1993, there is disclosed a read-modify-write operation which occurs in one memory cycle in a dual port static memory.
In U.S. Pat. No. 5,258,952, by T. A. Coker et al, which issued on Nov. 2, 1993, there is disclosed a read/write memory having time-out control of its peripheral circuitry wherein two delay stages of different length are used, the shorter delay stage being used to define the time-out in a read operation and the longer delay stage being used to define the time-out in a write operation.